1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) which utilizes a magnetoresistive effect.
2. Description of the Related Art
In recent years, many memories which store data by new principles have been proposed. One of them is a magnetic random access memory which utilizies the tunneling magnetoresistive (to be referred to as TMR hereinafter) effect.
As a proposal for a magnetic random access memory, for example, Roy Scheuerlein et al, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC2000 Technical Digest, p. 128 is known.
A magnetic random access memory stores “1”- and “0”-data using MTJ (Magnetic Tunnel Junction) elements. As the basic structure of a MTJ element, an insulating layer (tunneling barrier) is sandwiched between two magnetic layers (ferromagnetic layers). However, various kinds of MTJ element structures have been proposed to, e.g., optimize the MR (MagnetoResistive) ratio.
Data stored in the MTJ element is determined on the basis of whether the magnetizing states of the two magnetic layers are parallel or antiparallel. “Parallel” means that the two magnetic layers have the same magnetizing direction. “Antiparallel” means that the two magnetic layers have opposite magnetizing directions.
Normally, one (fixed layer) of the two magnetic layers has an antiferromagnetic layer. The antiferromagnetic layer serves as a member for fixing the magnetizing direction of the fixed layer. In fact, data (“1” or “0”) stored in the MTJ element is determined by the magnetizing direction of the other (free layer) of the two magnetic layers.
When the magnetizing states in the MTJ element are parallel, the tunneling resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the MTJ element is minimized. For example, this state is defined as a “1”-state. When the magnetizing states in the MTJ element are antiparallel, the tunneling resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the MTJ element is maximized. For example, this state is defined as a “0”-state.
Currently, various kinds of cell array structures have been examined for a magnetic random access memory from the viewpoint of increasing the memory capacity or stabilizing write/read operation.
For example, currently, a cell array structure in which one memory cell is formed from one MOS transistor and one MTJ element is known. Additionally, a magnetic random access memory which has such a cell array structure and stores 1-bit data using two memory cell arrays so as to realize stable read operation is also known.
However, in these magnetic random access memories, it is difficult to increase the memory capacity. This is because one MOS transistor corresponds to one MTJ element in these cell array structures.
As a magnetic random access memory which needs no MOS transistors in the memory cell array, a cross-point cell array structure is conventionally known. A cross-point cell array structure has a simple structure with an MTJ element being arranged at the inter-connection of a word line and a bit line. As a characteristic feature, no select transistor is arranged in the memory cell array.
According to the cross-point cell array structure, the memory cell size can be reduced because no select MOS transistors are used. As a consequence, the memory capacity can be increased.
For example, when the minimum size of design rule is defined as “F”, the size of a memory cell formed from a select MOS transistor and MTJ element is 8F2. However, a memory cell including only an MTJ element is 4F2. That is, the memory cell including only an MTJ element can realize a cell size about ½ that of the memory cell formed from a select MOS transistor and MTJ element.
However, when a magnetic random access memory is formed by employing a cross-point cell array structure, there is posed a problem of breakdown of the insulting layer (tunneling barrier layer) of a TMR (MTJ) element in write operation.
More specifically, in the cross-point cell array structure, an MTJ element is arranged at the intersection of a word line and a bit line while being in contact with them. Write currents having the same value are supplied to the word line and bit line (the directions of the write currents supplied to the word line and bit line change in accordance with the data value) to generate a magnetic field. The direction of magnetization of the MTJ element arranged between the word line and the bit line is thus determined.
The word line and bit line have interconnection resistances. The value of the interconnection resistance across the word line and bit line increases as they become long. That is, when the write current is flowing, the potential at a position close to the driver of the word line or bit line is higher than that at a position close to the sinker of the word line or bit line.
Hence, in write operation, a potential difference may be generated across the MTJ element in accordance with its position. This potential difference may cause voltage stress on the tunneling barrier layer of the MTJ element and then dielectric breakdown of the tunneling barrier layer.
This problem will be described in detail.
An MTJ element (worst case) which is arranged at a position closest to a word line driver WD (farthest from a word line sinker WS) and closest to a bit line sinker BS (farthest from a bit line driver BD), as shown in FIG. 107, will be examined.
The potential at the word-line-side end portion of the MTJ element is, e.g., Vp because the end portion is in contact with the word line at a position closest to the word line driver WD. On the other hand, the potential at the bit-line-side end portion of the MTJ element is, e.g., Vp-α because the end portion is in contact with the bit line at a position farthest from the bit line driver BD, and a voltage drop occurs due to an interconnection resistance r of the bit line.
That is, the potential of the bit-line-side end portion of the MTJ element is lower than that of the word-line-side end portion by α. As a result, the potential difference α is generated across the MTJ element arranged at the closest to the word line driver WD and bit line sinker BS.
Assume that dielectric breakdown of the tunneling barrier layer is caused by an electric field more than 10 [MV/cm] at a very high probability.
When the sheet resistance of the word line and bit line is 100 [mΩ], and the size of the memory cell array is 1750 (1.75 kilo) cells×1750 (1.75 kilo) cells, the interconnection resistance r from one end to the other end of the word line or bit line is as follows.
In the cross-point cell array structure, memory cells are arranged along the word lines and bit lines from one end to the other end of each of them. When a memory cell has a minimum process size (design rule) in the direction in which the word line or bit line runs, the pitch between the memory cells in that direction is also set to the minimum process size (pitch).
That is, the length of a word line or bit line corresponds to an array of 1750×2 memory cells. Hence, the interconnection resistance r from one end to the other end of the word line or bit line is 350 [Ω] (when the memory cell array becomes large, the word lines and bit lines become long, and the interconnection resistance r increases).
When the interconnection resistance r is 350 [Ω], and a write current Ip is 2 [mA], a potential difference of 0.7 (=0.002×350) [V] is generated across each of the word lines and bit lines.
When the thickness of the tunneling barrier layer of the MTJ element (when the MTJ element has a plurality of tunneling barrier layers, the total thickness of the tunneling barrier layers) is 0.7 [nm], and the potential difference across the MTJ element is 0.7 [V], an electric field of 10 [MV/cm] is generated in the MTJ element.
To avoid dielectric breakdown of the tunneling barrier layer under the above conditions, the size of one memory cell array surrounded by the word line driver/sinker and bit line driver/sinker must be set to 1.75 kilo×1.75 kilo or less.
As described above, in the cross-point cell array structure, when dielectric breakdown of the tunneling barrier layer of the MTJ element in write operation is taken into consideration, the upper limit of the memory cell array size is determined. Hence, the degree of integration of MTJ elements cannot be sufficiently increased.
In addition, the write current Ip does not always flow to the word line or bit line. The write current Ip is supplied to the word line or bit line only in the write operation. That is, the potential at a position closest to the word line or bit line sometimes exceeds Vp due to overshoot phenomenon.
In consideration of this overshoot phenomenon, an electric field more than 10 [MV/cm] may be generated in the MTJ element under the above conditions.
Assume that the sheet resistance of the word line and bit line, the write current Ip, and the thickness of the tunneling barrier layer are constant. In this case, to avoid probable generation of an electric field more than 10 [MV/cm] in the MTJ element at a high possibility, the memory cell array size must be further reduced to decrease the voltage drop amount due to the interconnection resistance r of the word line or bit line.
For example, overshoot of the potential on the word line or bit line will be examined under the above conditions. The upper limit size of one memory cell array must be decreased from 3 mega (=1.75 kilo×1.75 kilo) to 1.5 mega.
A clamp circuit which clamps the potential of the word line or bit line may be newly arranged as a peripheral circuit of the memory cell array to prevent the overshoot/undershoot phenomenon.
In this case, however, the size of the peripheral circuits increases as the clamp circuit is added. In addition, the clamp circuit has a function of suppressing abrupt increase/decrease in potential of the word line or bit line. For this reason, changing the potential of the word line or bit line to Vp takes a long time, resulting in a decrease in write speed.